This invention relates generally to data synchronizers which attempt to optimize the synchronization of sample timing to a sequence of data symbols in a receiver portion of a modem. Specifically, the present invention relates to a timing error estimator which successfully operates on a wide variety of modulation schemes.
Various timing error estimators which work with a wide variety of modulation schemes are known. For example, a "maximum likelihood" timing error estimator represents an optimum approach to the generation of a timing error signal. In theory, the maximum likelihood method may provide acceptable results, but this method is too computationally intensive for practical use in most applications.
A "squaring" timing estimator represents another technique. This technique is based upon filtering and squaring a data stream input signal to generate a sinusoidal component with a frequency equal to the symbol rate. Timing error estimation is then accomplished by heterodyning this sinusoidal component with a local oscillator and low pass filtering. An "early/late gate" timing estimator represents yet another approach. This scheme produces a timing error estimate by integrating over two half periods of each symbol pulse, and subtracting the results. The sign of the difference is then corrected according to the polarity of the pulse.
Both the squaring and early/late gate timing estimators are less computationally intensive than the maximum likelihood timing estimator. However, each of the squaring and early/late gate timing estimators achieve undesirably poor performance results in terms of linearity and estimation noise.